If a transmitter and a receiver are interchanging data via a transmission system, their respective local clock generators must be synchronized with each other or with a global clock.
Local clock generators of components of a transmission system are typically selected to provide a clock signal having the same nominal frequency. However, due to jitter and drift effects caused internally, inter alia, by temperature variations and ageing, almost unavoidably phase differences, at least temporally, between the clock signals of any two local clock generators in the transmission system. Systems with nominally identical clock frequencies but small frequency and phase deviations are also referred to as plesiochronous systems. The clock generation circuit and its principle of operation described in this specification are related to such plesiochronous systems.
Synchronization in a plesiochronous system is a matter of balancing the phase drifts between the local clock signals caused by slightly differing clock frequencies. Conventionally, these phase drifts are compensated for by analog and/or digital phase-locked loop circuits, or PLLs. Another application for PLL circuits is management of board-level skew. As faster switching technologies have become available, it has become necessary to use such circuits to minimize skew within various printed circuit boards, or PCBs, of an apparatus, or even within a single printed circuit board.
A PLL detects possible phase shifts between the frequency of a reference input signal and the frequency of a controllable signal source and modifies the frequency and the phase of the controllable signal source until the phase difference between the reference input signal and the signal of the controllable signal source is eliminated.
FIG. 1 shows the main blocks used in a PLL e.g. in a receiver. Reference signal fref is applied to a first input of phase detector PD. Output signal fRX of controllable oscillator VCO (voltage controlled oscillator) located in the receiver is applied to a second input of phase detector PD. The resulting signal Δφ indicative of the phase difference is applied to the controllable oscillator VCO via a loop filter LF and controls the frequency of the controllable oscillator VCO. The loop filter LF reduces the effects of spurious variations and also slows down the response of the VCO so as to limit unwanted oscillation of the control signal, which may cause unwanted jitter in the VCO's output signal. However, this generally slows down the speed of tracking frequency drifts. Typically, elements of the circuit adding significant delay are included in the feedback loop, such that the effective delay can be minimized or even eliminated.
PLLs, however, are relatively costly and difficult to integrate into digital ICs. The controllable oscillator VCO often is build discrete or manually trimmed to the desired accuracy, which makes such components expensive. Also, additional analog components are required, resulting into solutions that are sensitive to noise and temperature, especially if very accurate frequencies with small jitter are to be generated.
An alternative to analog PLLs are digital PLL circuits that use a digitally controlled oscillator, or DCO. DCOs are often implemented by an oscillator providing a high frequency output signal and an N-divider. The N-divider divides the high frequency input clock, e.g. by means of one or more counters, into an output clock signal having a lower frequency. However, even designing and operating a digital PLL can be a challenging task if very high output frequencies are to be synthesized, because at least a factor of three between the input frequency and the divided frequency is typically required in order to provide sufficiently small steps for regulation, and for decoupling the high frequency clock and the buffered output clock derived from the high frequency clock. In particular in FPGAs (field programmable gate arrays), which typically use and provide lower clock frequencies than ASICs (application specific integrated circuits), it is often not possible to implement DCOs capable of providing the required high frequency.
Delay locked loop circuits, or DLLs, are an alternative to PLLs. A DLL takes a, e.g. locally generated, clock input and dynamically performs a phase shift using one or more selectable or adjustable delay elements for providing a desired delay time. A delay element can be for instance an inverter pair having a predetermined propagation delay. Modern DLLs are able to combine some of the delay elements dynamically, or are able to dynamically adjust the delay. DLLs of this kind are commercially available and described e.g. in the data sheet and user guide of the Xilinx Virtex-5 FPGA, available under http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf, http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.
Compared to PLLs a DLL is able to eliminate phase differences much faster. However, the maximum delay is ultimately limited, e.g. up to 256 basic delay steps using an 8-bit counter. This results in commercially available DLLs not being capable of balancing continuous frequency drifts, because this requires continuous phase balancing during run time. In other words, balancing a persistent frequency difference between two or more clocks requires an infinite number of delay elements. Shortly after the process starts, any commercially available DLL having a finite maximum delay would run into its limitation, due to the finite maximum phase shift it can provide, resulting in an output clock signal that cannot be shifted any more. If this occurs, the frequency synchronization will be lost, because the clock in a receiver has to permanently follow the transmitter clock frequency. For this reason, DLLs are often only used for setting an initial delay within a circuit, so as to compensate for a known delay inside the circuit that is generally not variable.
US 2009/0267665 A1 discloses a DLL circuit having two DLLs, one of which selectively provides an output signal through a multiplexer. The DLLs are fed with respective inverted clock signals, i.e. a clock signal having a phase offset of 180°. However, the known DLL circuit is used in a system, in which a single system clock is provided locally and concurrent with data that is processed using the system clock, and in which the delay does not vary, because it is caused by different physical path lengths of clock and data lines. In other words, the known circuit is used for compensating run time differences in clock and data signals within the same apparatus. The known DLL circuit switches over between the two DLLs only during initial set-up, in the case of the delay provided by the first DLL is insufficient, i.e. switching over between the two DLLs occurs only once. A single switchover is sufficient, because the physical path lengths are constant, and do not change during runtime. Also, a single switch over process occurring only during an initiation phase of a circuit greatly reduces the danger of glitches, or generally clock pulses not conforming to a required shape, duration, or the like, having a detrimental influence on the operation of a circuit.